面向大数据的异构内存系统

王孝远; 廖小飞; 刘海坤; 金海

doi:10.11959/j.issn.2096-0271.2018037

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面向大数据的异构内存系统

专题：大数据驱动的智能计算体系架构 | 更新时间：2024-06-03

- 面向大数据的异构内存系统
- Big data oriented hybrid memory systems
- 大数据 2018年4卷第4期页码：2018037
- 作者机构：
- 作者简介：
  
  [ "王孝远（1990-），男，华中科技大学计算机学院博士生，主要研究方向为内存计算、操作系统等。" ]
  [ "廖小飞（1978-），男，华中科技大学计算机学院教授，主要研究方向为内存计算、系统软件、分布式系统等。" ]
  [ "刘海坤（1981-），男，华中科技大学计算机学院副教授，主要研究方向为内存计算、虚拟化技术等。" ]
  [ "金海（1966-），男，华中科技大学计算机学院教授，主要研究方向为大数据处理、计算机系统结构、信息安全等。" ]
- 基金信息：
  
  国家重点研发计划基金资助项目;The National Key Research and Development Program of China(2017YFB100160);国家自然科学基金资助项目;The National Natural Science Foundation of China(61672251);国家自然科学基金资助项目;The National Natural Science Foundation of China(61732010);国家自然科学基金资助项目;The National Natural Science Foundation of China(61628204)
- DOI：10.11959/j.issn.2096-0271.2018037
  中图分类号： TP31
- 网络首发：2018-07，
  
  纸质出版：2018-07-15
- 稿件说明：
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王孝远, 廖小飞, 刘海坤, 等. 面向大数据的异构内存系统[J]. 大数据, 2018,4(4):2018037.

Xiaoyuan WANG, Xiaofei LIAO, Haikun LIU, et al. Big data oriented hybrid memory systems[J]. Big Data Research, 2018, 4(4): 2018037.
王孝远, 廖小飞, 刘海坤, 等. 面向大数据的异构内存系统[J]. 大数据, 2018,4(4):2018037. DOI： 10.11959/j.issn.2096-0271.2018037.

Xiaoyuan WANG, Xiaofei LIAO, Haikun LIU, et al. Big data oriented hybrid memory systems[J]. Big Data Research, 2018, 4(4): 2018037. DOI： 10.11959/j.issn.2096-0271.2018037.

摘要

受限于DRAM和新型非易失性存储器（non-volatile memory，NVM）的缺陷，单纯的DRAM 或者NVM 难以满足大数据应用对内存系统容量以及功耗提出的高要求。因此如何将DRAM和NVM组合成异构内存系统并进行高效的管理、准确的评估，是当今学术界和工业界面临的主要挑战。从体系结构、系统软件、编程模型以及应用等方面对面向大数据的异构内存系统进行分析与研究，提出了一系列异构内存系统的优化方法，如层次化异构内存架、片上缓存管理、访存调度、能耗管理、虚实地址转换和面向对象的内存分配与迁移机制等，并实现了原型系统进行验证。

Abstract

Big data applications put more pressure on memory system in the aspect of capacity and power consumption.However

limited by the shortcomings of DRAM and non-volatile memory(NVM)

memory consists of single medium like DRAM or NVM is not competent for the requirements of big data applications.Thus

how to effectively design

efficiently manage and accurately evaluate the hybrid memories consist of DRAM and NVM are the major challenges that the academia and industry face today.The challenges of hybrid memory systems for big data processing from the perspective of computer architecture

system software

programming model and application were analyzed

and several solutions and optimizations were correspondingly provided

such as on-chip cache management

parallel processing

memory access scheduling

energy management

virtual-to-physical address translation

object-level memory allocation and migration mechanisms.Meanwhile

a number of prototypes to validate the effectiveness and efficiency of these proposals were developed.

关键词

Keywords

references

QURESHI M K , SRINIVASAN V , RIVERS J A . Scalable high performance main memory system using phase-change memory technology [C ] // The 36th Annual International Symposium on Computer Architecture,June 20-24,2009,Austin,USA . New York:ACM Press , 2009 : 24 - 33 .

MLADENOV R , . An efficient non-volatile main memory using phase change memory [C ] // The 13th International Conference on Computer Systems and Technologies,June 22-23,2012,Ruse,Bulgaria . New York:ACM Press , 2012 : 45 - 51 .

PARK H , YOO S , LEE S . Power management of hybrid DRAM/PRAM based main memory [C ] // The 48th Design Automation Conference,June 5-10,2011,San Diego,USA . New York:ACM Press , 2011 : 59 - 64

RAMOS L E , GORBATOV E , BIANCHINI R . Page placement in hybrid memory systems [C ] // The International Conference on Supercomputing,May 31-June 4,2011,Tucson,USA . New York:ACM Press , 2011 : 85 - 95

WEI W , JIANG D , MCKEE S A , et al . Exploiting program semantics to place data in hybrid memory [C ] // The 2015 International Conference on Parallel Architecture and Compilation,October 18-21,2015,San Francisco,USA . Piscataway:IEEE Press , 2015 : 163 - 173 .

XU J , SWANSON S . NOVA:a logstructured file system for hybrid volatile/non-volatile main memories [C ] // The 14th USENIX Conference on File and Storage Technologies,February 22-25,2016,Santa Clara,USA . San Francisco:USENIX Association , 2016 : 323 - 338 .

LIU H K , CHEN Y J , LIAO X F , et al . Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures [C ] // International Conference on Supercomputing (ICS '17),June 14-16,2017,Chicago,USA . New York:ACM Press , 2017 .

CHEN D , JIN H , LIAO X , et al . MALRU:miss-penalty aware LRU-based cache replacement for hybrid memory systems [C ] // Design,Automation ＆Test in Europe Conference ＆ Exhibition (DATE),March 27-31,2017,Lausanne,Switzerland . Piscataway:IEEE Press , 2017 : 1086 - 1091 .

ZHANG J , LIAO X , JIN H , et al . An optimal page-level power management strategy in PCM–DRAM hybrid memory [J ] . International Journal of Parallel Programming , 2017 , 45 ( 1 ): 4 - 16 .

DHIMAN G , AYOUB R , ROSING T . PDRAM:a hybrid PRAM and DRAM main memory system [C ] // The 46th Annual Design Automation Conference,July 26-31,2009,San Francisco,USA . Piscataway:IEEE Press , 2009 : 664 - 669 .

LEE S , BAHN H , NOH S H . Clockdwf:a write history-aware page replacement algorithm for hybrid pcm and dram memory architectures [J ] . IEEE Transactions on Computers , 2014 , 63 ( 9 ): 2187 - 2200 .

ZHANG W , LI T . Exploring phase change memory and 3D die-stacking for power/thermal friendly,fast and durable memory architectures [C ] // The 18th International Conference on Parallel Architectures and Compilation Techniques,September 12-16,2009,Raleigh,USA . Piscataway:IEEE Press , 2009 : 101 - 112 .

LOH G H , HILL M D . Efficiently enabling conventional block sizes for very large die-stacked DRAM caches [C ] // The 44th IEEE/ACM International Symposium on Microarchitecture,December 3-7,2011,Porto Alegre,Brazil . Piscataway:IEEE Press , 2011 : 454 - 464 .

PARK Y , PARK S K , PARK K H . Linux kernel support to exploit phase change memory [C ] // Linux Symposium,July 13-16,2010,Ottawa,Canada.[S.l.:s.n] . 2010 : 217 - 224 .

LIU M X , ZHANG M X , CHEN K , et al . DudeTM:building durable transactions with decoupling for persistent memory [C ] // The 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '17),April 8-12,2017,Xi'an,China . New York:ACM Press , 2017 : 329 - 343 .

WANG Z , SHAN S C , CAO T , et al . WADE:writeback-aware dynamic cache management for NVM-based main memory system [J ] . ACM Transactions on Architecture and Code Optimization , 2013 , 10 ( 4 ): 1 - 21 .

WEI W , JIANG D J , XIONG J , et al . HAP:hybrid memory-aware partition in shared last-level cache [J ] . ACM Transactions on Architecture and Code Optimization , 2017 , 14 ( 3 ): 1 - 25 .

SANCHEZ D , KOZYRAKIS C . ZSim:fast and accurate microarchitectural simulation of thousand-core systems [C ] // The 40th Annual International Symposium on Computer Architecture,June 23-27,2013,Tel-Aviv,Israel . New York:ACM Press , 2013 : 475 - 486 .

POREMBA M , ZHANG T , XIE Y . NVMain 2.0:a user-friendly memory simulator to model (non-)volatile memory systems [J ] . IEEE Computer Architecture Letters , 2015 , 14 ( 2 ): 140 - 143 .

LUK C K , COHN R , MUTH R , et al . Pin:building customized program analysis tools with dynamic instrumentation [J ] . SIGPLAN Not , 2005 , 40 ( 6 ): 190 - 200 .

ROSENFELD P , COOPER-BALIS E , JACOB B . DRAMSim2:a cycle accurate memory system simulator [J ] . IEEE Computer Architecture Letters , 2011 , 10 ( 1 ): 16 - 19 .

YOON H , MEZA J , AUSAVARUNGNIRUN R , et al . Row buffer locality aware caching policies for hybrid memories [C ] // 2012 IEEE 30th International Conference on Computer Design (ICCD),September 30October 3,2012,Montreal,Canada . Piscataway:IEEE Press , 2012 : 337 - 344 .

DUAN Z H , LIU H K , LIAO X F , et al . HME:a lightweight emulator for hybrid memory [C ] // Design,Automation ＆ Test in Europe Conference ＆ Exhibition (DATE),March 19-23,Dresden,Germany.[S.l.:s.n] . 2018 : 1375 - 1380 .

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